1. Field of the Invention
The invention relates to an electrically writable non-volatile semiconductor memory device, particularly to a circuit for generating a drain voltage to be applied to a specific memory cell during read operation.
This application is a counterpart of Japanese patent application. Serial Number 291116/2002, filed Oct. 3, 2002, the subject matter of which is incorporated herein by reference.
2. Description of Related Art
There are following related related arts.                JP 2000-11668A        JP 1994-215585A        JP 1994-342598A        
FIG. 2 is a circuit configuration showing an example of a conventional semiconductor memory device.
This semiconductor memory device is an electrically writable non-volatile memory, and has a plurality of memory arrays MAk (k=0 to p). Each of the memory array MAk has the same configuration, and has a plurality of word lines WLi (I=0 to m), which are arranged in parallel with one another, and a plurality of drain lines DLj (j=0 to n) which are arranged to intersect the word lines WLi, wherein a plurality of source lines SLj are arranged in parallel with one another between the drain lines DLj and DLj+1.
Memory cells MCEi, j are arranged at the point of intersection between the word lines WLi, drain lines DLj, and source lines SLj, and memory cells MCOi, j are arranged at the point of intersection between the word lines WLi, drain line DLj+1, and source lines SLj. Numerical subscripts such as i, j and so forth are omitted in the following description except in the case where constituting components are specified concretely.
The memory cells MCE, MCO are a field-effect transistor (hereinafter referred to as FET) having a floating gate, wherein a control gate, a drain and a source of the FET are respectively connected to the corresponding word lines WL and drain lines DL, and source lines SL.
In the case where an electric charge is absent on each floating gate of the memory cells MCE, MCO, a threshold voltage of the FET is lowered so that the FET turns ON (e.g., memory content “1”), while in the case where the electric charge is present, the threshold voltage of the FET is increased so that the FET turns OFF (e.g., memory content “0”). Since the floating gate is isolated from other electrodes, if a high voltage is applied to the word lines WL to accumulate the electric charge, the memory content is stored even upon power-down.
Each of the drain lines DLj are connected to the drain voltage MCD via an n-channel MOS transistor (hereinafter referred to as NMOS). An even numbered selection signal SEV is supplied to each gate of NMOS1j of even numbered and an odd numbered selection signal SOD is supplied to each gate of the NMOS1j of odd numbered, wherein they are subjected to on-off control.
Further, the source lines SLj are connected to bit lines BLj via an NMOS2j which are in common subjected to on-off control in response to a memory array selection signal MAS. The source lines SLj of the memory arrays MA are connected to the bit lines BLj via the NMOS2j.
Still further, the bit line BL0 is connected to a data line DL0 via an NMOS30, and a bit line BLn is connected to a data line DL1 via an NMOS4n. Further, bit lines BL1 to BLn−1 are connected in common to the data lines DL0, DL1 via NMOS 31 to NMOS3n−1 and NMOS 41 to NMOS4n−1. Each of the NMOS 3j and NMOS4j+1 is subjected to on-off control in response to a bit line selection signal Yj, respectively.
The data lines DL0, DL1 are connected to sense amplifiers (SA) 50, 51, and data D0, D1 each having a predetermined logical level are outputted from the sense amplifiers 50, 51.
The selection signal relative to the word lines WL of each memory array MA, the even numbered selection signal SEV, the odd numbered selection signal SOD, and the memory array selection signal MAS are supplied from corresponding memory array driving circuits MADRs in response to word line selection signals XP0 to XPm, memory array selection signal MAS0 to MASp, and even and odd numbered selection signals YEV and YOD which are outputted from an address decoder, not shown, respectively. Bit line selection signals Y relative to the NMOSs 3, 4 are supplied from the address decoder. Meanwhile, the drain voltage MCD to be applied in common to each memory array MA is generated by a drain voltage generator 10.
The drain voltage generator 10 generates the drain voltage MCD (e.g., 1.2V) which is sufficiently lower than a power supply voltage VCC (e.g., 3V) for read operation of each memory array MA when the semiconductor memory device is rendered in an active state in response to a chip selection signal /CE (“/” is inverting symbol).
The drain voltage generator 10 has a p-channel MOS transistor (hereinafter referred to as PMOS)11 and an NMOS12 which are controlled in conductive state by the chip selection signal /CE. A source of the PMOS11 is connected to the power supply voltage VCC, and a drain thereof is connected to a node N1. A drain of the NMOS12 is connected to the node N1 and a source thereof is connected to the ground voltage GND.
Further, a drain of an NMOS13 is connected to the node N1, and a source and a gate thereof are connected to the ground voltage GND and a node N2. A source of an NMOS14 is connected to the node N2, and a gate of the NMOS14 is connected to the node N1. A drain of the NMOS14 is connected to the power supply voltage VCC via a PMOS15 a gate of which is connected to the ground voltage GND. The drain voltage MCD is outputted from the node N2.
An operation of the conventional semiconductor memory device is described next.
With the semiconductor memory device having the foregoing configuration, in the case where read operation is effected relative to the memory cell, the chip selection signal /CE goes “L”, thereby setting an active state. Accordingly, the PMOS11 and NMOS12 turn ON and OFF, respectively, and the voltage of the node N1 goes “H”. When the voltage of the node N1 goes “H”, the NMOS14 turns ON, and the node N2 is connected to the power supply voltage VCC via the NMOS14 and the PMOS15, thereby increasing the voltage of the node N2. The voltage of the node N2 is fed back to the gate of the NMOS13, so that the NMOS13 turns ON.
As a result, a voltage obtained by dividing the power supply voltage VCC by the PMOS11 and the NMOS13 is outputted to the node N1. The voltage of the node N1 is further applied to the gate of the NMOS14. With such a feedback loop, the drain voltage MCD outputted from the node N2 becomes about 1.2 V which is sufficiently lower than the power supply voltage VCC. Accordingly, there is no fear that data is erroneously written in the memory cell during read operation, so that the memory content is not changed but held in the memory cell.
Meanwhile, in the case where no read operation is effected relative to the semiconductor memory device, the chip selection signal /CE goes “H”, thereby setting a standby state. Accordingly, the PMOS11 and the NMOS12 of the drain voltage generator 10 turn OFF and ON, respectively, and the voltage of the node N1 becomes the ground voltage GND. When the voltage of the node N1 becomes the ground voltage GND, the NMOS14 turns OFF to set the node N2 in an open state. As a result, the drain voltage MCD is not outputted but substantially goes the ground voltage GND owing to leakage resistance and so forth. Accordingly, a drain current does not flow to each memory array MA, thereby reducing a current consumption in the standby state.
However, the conventional semiconductor memory device has following problems.
If the number of memory arrays and bit lines increase as a memory capacity increases, the entire length of wires through which the drain voltage MCD is supplied lengthens, thereby increasing a load caused by a parasitic capacitance of the wires and the like. Accordingly, if a standby state is switched to an active state in response to the chip selection signal /CE, the rising of the drain voltage MCD to be applied to each memory array MA delays, causing a problem that a normal read operation is not effected.